(1) Field of the Invention
The invention relates to the testing of electronic equipment.
(2) Description of the Related Art
In the manufacturing of electronic equipment, it is beneficial to test the proper operation of the manufactured equipment in order to maintain an expected level of quality. Testing may be performed on individual electronic components, subsystems, and complete systems. Since testing of subsystems and systems involves testing of interconnections between components, techniques have been developed to facilitate such testing.
One example of a technique for testing of interconnections between components is referred to as boundary scan. Boundary scan involves providing registers and supporting circuitry in components in accordance with an established boundary scan standard, such as Institute of Electrical and Electronics Engineers, Inc. (IEEE) Standard 1149.1, which was developed based on a proposal by the Joint Test Action Group (JTAG). A component with provisions for boundary scan may be configured using a test access port (TAP) to output or receive as input digital signals on the input/output (I/O) pins of the component. The TAP includes five pins consisting of the following: a test data input (TDI), a test data output (TDO), a test mode select (TMS), a test clock (TCK), and a test reset (TRST). Testing of an interconnection between two components is accomplished by configuring a first component to output a signal of a specified logic level and configuring a second component to receive as an input that signal and to identify the received logic level of that signal. An external test controller compares the logic level of the output signal with the received logic level of the input signal to determine if the interconnection between the components is passing the signal properly. The registers provided for boundary scan are configured to operate as shift registers, allowing the data of the output signal and the input signal to be shifted through the boundary scan chain, both within a component and among several components.
However, as the data rates with which components communicate increase, the ability to provide for boundary scan testing becomes increasingly difficult. Yet, such increased data rates require even higher standards of performance from the interconnections for which such testing is frustrated. Without an effective testing technique, assembly yield would be decreased, and total manufacturing cost would be increased. Also, some IC devices, such as memory devices, often don't support the additional pins due to package and silicon cost and complexity associated with the boundary scan macro. Thus, a technique is needed to provide a capability of advanced testing in modern electronic equipment.
The use of the same reference symbols in different drawings indicates similar or identical items.